Microelectronic substrates and substrate assemblies typically include a semiconductor material having features, such as memory cells, that are linked with conductive lines. The conductive lines can be formed by first forming trenches or other recesses in the semiconductor material and then overlaying a conductive material (such as a metal) in the trenches. The conductive material is then selectively removed to leave conductive lines or vias extending from one feature in the semiconductor material to another.
FIG. 1 is a partially schematic illustration of a portion of a microelectronic substrate 10 having a conductive line formed in accordance with the prior art. The microelectronic substrate 10 includes an aperture or recess 16 in an oxide material 13. A barrier layer 14, formed from materials such as tantalum or tantalum compounds, is disposed on the microelectronic substrate 10 and in the aperture 16. A conductive material 15, such as copper, is then disposed on the barrier layer 14. The barrier layer 14 can prevent copper atoms from migrating into the surrounding oxide 13.
In a typical existing process, two separate chemical-mechanical planarization (CMP) steps are used to remove the excess portions of the conductive material 15 and the barrier layer 14 from the microelectronic substrate 10. In one step, a first slurry and polishing pad are used to remove the conductive material 15 overlying the barrier layer 14 external to the aperture 16, thus exposing the barrier layer 14. In a separate step, a second slurry and a second polishing pad are then used to remove the barrier layer 14 (and the remaining conductive material 15) external to the aperture 16. The resulting conductive line 8 includes the conductive material 15 surrounded by a lining formed by the barrier layer 14.
One drawback with the foregoing process is that high downforces are typically required to remove copper and tantalum from the microelectronic substrate 10. High downforces can cause other portions of the microelectronic substrate 10 to become dished or eroded, and/or can smear structures in other parts of the microelectronic substrate 10. A further drawback is that high downforces typically are not compatible with soft substrate materials. However, it is often desirable to use soft materials, such as ultra low dielectric materials, around the conductive features to reduce and/or eliminate electrical coupling between these features.